Download 60-GHz CMOS Phase-Locked Loops by Hammad M. Cheema, Reza Mahmoudi, Arthur H.M. van Roermund PDF

By Hammad M. Cheema, Reza Mahmoudi, Arthur H.M. van Roermund

The promising excessive info price instant functions at millimeter wave frequencies generally and 60 GHz particularly have received a lot cognizance lately. even though, demanding situations on the topic of circuit, structure and measurements in the course of mm-wave CMOS IC layout need to be triumph over prior to they could develop into plausible for mass market.

60-GHz CMOS Phase-Locked Loops concentrating on phase-locked loops for 60 GHz instant transceivers elaborates those demanding situations and proposes recommendations for them. The method point layout to circuit point implementation of the full PLL, besides separate implementations of person elements resembling voltage managed oscillators, injection locked frequency dividers and their mixtures, are integrated. in addition, to fulfill a couple of transceiver topologies at the same time, flexibility is brought within the PLL structure through the use of new dual-mode ILFDs and switchable VCOs, whereas reusing the low frequency parts on the related time.

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Extra resources for 60-GHz CMOS Phase-Locked Loops

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The loop bandwidth of 4 MHz forms the “knee” in the phase noise curve. The in-band phase noise, say at 100 kHz is dominated by PFD and charge pump and is about À110 dBc/Hz whereas out-ofband noise, say at 30 MHz is dominated by the VCO and is À128 dBc/Hz. These values provide a first estimate about the expected phase noise performance. However, the simulation does not include all noise mechanisms which are present at circuit level. Similar simulations are carried out with a 60 GHz front-end by replacing the VCO and modifying the overall division ratio.

The related concept of transfer functions, which describe the s-domain relation between input and output of a linear circuit, is used to analyze the open-loop and closed-loop characteristics of the PLL. A simplified s-domain representation of the synthesizer is shown in Fig. 8. The phase-frequency detector and charge-pump are merged into one block represented by a transfer parameter, KPFD (equal to Icp/2p). The impedance of the second-order loop filter is shown as ZLPF. The VCO conversion gain, KVCO, represents the sensitivity of VCO frequency with tuning voltage in rad/(s  V).

For instance, the measurement cables may be coaxial while the wafer has micro-strip or coplanar waveguide based transmission lines carrying the RF sign-als. The selection of the probe, based on operating frequency range and layout of the chip is an important factor as incorrect probes can introduce losses degrading the overall measurements. The probe position and alignment (in z-direction) on the bond-pads is critical for correct mm-wave measurements especially during calibration and de-embedding procedures (explained in next section).

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